Highly integrated chips, which may have hundreds of millions of transistors, dissipate significant amounts of power which may cause severe overheating leading to possible thermal run-away and chip damage. The situation may be even worse where different chip areas dissipate different amounts of power due to different performance modes of the chip areas. For example, the same local block could dissipate either significant amounts of power or small amounts of power at different times based on the performance mode applicable to the particular local block.
It is possible to avoid overheating for such different local areas if information about local over-heating conditions for the different areas at different times is accumulated and processed. To accomplish this, a certain number of thermo-sensors must be placed at different local areas of the chip, to monitor the local area's temperature. The thermo-sensors would also require a single digital block, acting as a temperature controller, that could process data received from the various thermo-sensors data, and make certain predetermined decisions, such as decreasing clock speed, decreasing voltage supply level, increasing fan rotations, shutting-down a temporarily over-heated block, etc., in order to avoid permanent damage to the chip.
Such on-chip thermo-sensors must be accurate, Process/Voltage/Temperature (PVT) independent, and not be a burden to on-chip routing resources. Further, accurate temperature measuring methodologies must be applied. Unfortunately, existing on-chip thermo-sensors and measurement methods are not accurate. While these existing measurements and methodologies are leakage and PVT dependable, they can not provide accurate enough temperature data to avoid chip damage that may occur during high core activity.
There are several known solutions that the integrated circuit industry has utilized in an attempt to avoid chip thermal run-away and the damage that may result. One such solution employs an external thermo-sensor that may be fixed, for example by glue, on top of chip to be monitored. While this solution provides integrated circuit package temperature data, it does not have the needed accuracy, increases the external component cost, and is too slow to reflect fast temperature changes due to significant chip/package thermo-capacitor values.
A second known solution, descriptions of which are found throughout the industry literature, employs two internal diodes. This solution provides a technique of measuring temperature by comparing the voltage difference for the two diodes at different current densities, and following this difference with amplification. This solution has advantages over the top-of-chip sensor approach in that it provides a way of obtaining temperature data for local areas of the chip. However, the solution still has several significant disadvantages. First, the solution requires too much chip routing resources to place the two diodes in the different local areas of the chip and provide the necessary connections with the central digital block. Second, significant errors exist due to mismatches between the two diodes. Further, the diode mismatch error will be magnified by amplifier offset error causing the solution to be even less accurate.
The most progressive existing solution utilizes a single diode and a sample-and-hold architecture. The sample-and-hold architecture makes it possible to use only a single diode to sample, hold, and compare the difference between two diode voltage levels, which are based on two different current levels that are sent through the single diode. This solution also requires two capacitors, and ΔVbe ADC 111, and associated processing logic as illustrated in FIG. 1. Although this solution uses two external capacitors, thereby increasing the cost by adding external components, it is possible to implement the solution with two internal capacitors instead.
Although using only a single diode eliminates the problems associated with diode mismatch, and also eliminates complicated routing problems, this solution still presents several disadvantages. First, the sample-and-hold architecture can not provide the needed accuracy due to the leakage vulnerability of the switches and capacitors involved. Leakage currents, which are difficult to avoid for such on-chip switches, will degrade the circuit's “hold” mode data.
Additionally, high leakage current temperature dependence and mismatch renders a higher leakage error at higher temperature. Amplifier offset error as well as quantization error also worsens the accuracy of this solution.
Therefore, what is needed are methods and apparatuses for measuring temperature increases at the local block level with the required accuracy, and providing responses to undesirable temperature levels quickly enough to avoid thermal induced damage to the chip.